perf(ds4): reuse F16 KV in fused verification - #632

Summary

Add an opt-in --ds4-fused-verify-f16-kv path for single-device HIP DeepSeek V4 verification.

The existing explicit batched verifier converts the complete persistent F16 MLA cache to F32 on every speculative step. This path feeds the same raw and compressed rows directly from the F16 cache into the established explicit attention topology. It keeps F32 key-side accumulation through 512 attention rows to protect the short-context baseline, then avoids the full-cache conversion at longer contexts.

The attended row set, masks, and explicit attention operation order are unchanged. The option remains off by default and is rejected by the feature gate outside a monolithic HIP DeepSeek V4 backend. It can still change generated tokens because the verifier inputs are F16.

Published qualification patches:

• lucebox-ds4-fused-explicit-f16-kv.patch
• lucebox-ds4-explicit-f16-f32-attention.patch

Matched benchmark

Ryzen AI Max+ 395 / Radeon 8060S, ROCm 7.1.1, 100/100/100 W package limits, fixed-high GPU policy, ROCmFPX target, Q4RMFP4 DSpark draft, all six experts, q=4 fused verification, Q4_0 K/V. Each comparison used the same prompt and power policy.

The long-context decode gain is 37.2%; prefill is unchanged within run variance. A production composition including this path and the same 512-row F32 cutoff later passed 122,879-token 5/5 retrieval, 1.00 acceptance, and the 30/30 quality gate. The deployment-specific adaptive-prefill and graph-cache limits from that composition are intentionally not part of this PR.

Reproduction setup and benchmark definitions: https://github.com/pepuscz/strix-halo-deepseek-v4-flash

Validation

• Added placement feature-gate coverage; the pure feature-gate binary passes locally
• git diff --check
• The qualified ROCm 7.1.1 source composition built successfully and passed 353/354 server tests; the sole failure was the pre-existing MoeHybridStorageFixture::fractional_route_quota_rounds_over_the_batch expectation